1. Field of the Invention
This invention relates to the fabrication of integrated circuits which employ both bipolar and complementary field effect transistors on a common substrate, more typically known as BiCMOS processes. In particular, the invention provides a process in which the P- and N-type buried layers are self-aligned with each other, and in which the P- and N-type wells in an spitaxial layer are self-aligned with each other and substantially coplanar. Furthermore, the process of the invention enables the formation of polycrystalline silicon load resistors and double-diffused emitters for bipolar devices. The process also provides an improved technique for forming openings in passivation layers separating electrical conductors or electrical conductors from the substrate in such circuits.
2. Description of the Prior Art
Many different BiCMOS processes are now well known in the semiconductor fabrication industry. Such processes, however, suffer from a number of unfortunate disadvantages. Disadvantages of such processes involve the difficulty of aligning the P- and N-type buried layers in the substrate, as well as aligning and planarizing the P and N conductivity-type wells in the spitaxial layer disposed on the substrate.
Another disadvantage of prior art BiCMOS processes is the difficulty of fabricating polycrystalline resistors in structures manufactured utilizing the process. Because of the sequence of process steps, it typically has been difficult to accurately dope the polycrystalline silicon and obtain the desired resistance. Such limitations in the process technology unduly restrict the freedom of the circuit designer, and are therefore, undesirable.
Another disadvantage relates to the use of numerous layers of electrical interconnections, now well known in the fabrication of integrated circuits. For example, integrated circuits using two layers of polycrystalline silicon interconnections are well known, as are circuits using more than one metal layer. In the formation of such circuits, defects often arise where contact openings must be made through insulating layers to underlying regions, whether conductive or semiconductive.
As the density of active and passive devices on a given size integrated circuit continues to increases, the importance of forming reliable contact openings also increases. In the lower density circuits of the prior art, large areas were available for the formation of contacts, enabling the use of large openings, and relatively thick layers of metal or polycrystalline silicon connections. Because of the layer's thickness, difficulties in traversing steps or other nonlinearities in the underlying surface were minimized.
With the advent of increasingly large integrated circuits, for example, circuits containing a million or more transistors on a chip, very small feature sizes are required, lessening the ability to use large contact openings and thick layers of electrical connections. Accordingly, the provision of reliable electrical connections for such circuits has become increasingly difficult.
Furthermore, as device scaling continues to shrink feature sizes in integrated circuit technology, the formation of contacts becomes more difficult. In prior art processes, a wet-etch was typically employed which, due to its isotropic nature, provided a slope to the opening for good metal step coverage. The increasing density of circuits, however, often results in a wet-etch expanding the contact region to a point where when the metal or other conductor is deposited, shorts are created to adjacent conductive regions, once the opening is filled with metal.
Numerous techniques are well known for the fabrication of emitters in integrated circuits. For example, the formation of emitters using well known masking and diffusion or ion-implantation processes are well known. More recently, the fabrication of emitters from the out diffusion of impurities from doped overlying layers, such as polycrystalline silicon, has become well known.
Unfortunately, this aspect of the prior art processes suffer from a variety of disadvantages. The conventional diffusion/ion-implantation techniques require the formation of a mask and the introduction of impurities through openings in the mask. Because the mask must be accurately positioned with respect to surrounding portions of the transistor, or other surrounding regions, allowance must be made for alignment errors. This undesirably increases the size of the devices formed. Formation of emitters by out diffusion of impurities from doped polycrystalline silicon layers also suffers from several disadvantages. In particular, a very thin layer of silicon dioxide typically will be formed on the substrate from exposure of the substrate to air preceding and during formation of the emitter contact regions. This interface oxide undesirably increases the emitter series resistance. Additionally, the out diffusion process requires a very shallow base region because of the shallow emitter. Such shallow bases are well known to have high base resistance, thereby undesirably increasing switching speeds.